PORTE=0, LPUART0=0, LPUART1=0, PORTC=0, FLEXIO=0, LPTMR=0, PORTB=0, PORTA=0, PORTD=0
System Clock Gating Control Register 5
| LPTMR | Low Power Timer Access Control 0 (0): Access disabled 1 (1): Access enabled |
| PORTA | Port A Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTB | Port B Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTC | Port C Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTD | Port D Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTE | Port E Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART0 | LPUART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART1 | LPUART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FLEXIO | FlexIO Module 0 (0): Clock disabled 1 (1): Clock enabled |